1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device that has an interconnection layer containing Au and a bonding pad containing Al.
2. Description of the Related Art
A semiconductor device having a silicon substrate is commonly used as a high-power semiconductor device that is used for an inverter, a converter, or a switch of a switching regulator. In such a semiconductor device, which is usually provided as a semiconductor chip, a large amount of current flows through the bonding wires connected to the semiconductor chip, and therefore, the bonding wires are made of Al (aluminum) having low resistivity. Meanwhile, the interconnection layer and the bonding pad formed on a semiconductor chip having a silicon substrate is typically made of Al. As a result, bonding wires containing Al as a main component (hereinafter referred to as Al wires) are bonded to a bonding pad containing Al as a main component (hereinafter referred to as an Al pad).
In recent years, high-power semiconductor devices each having a III-V compound semiconductor layer containing GaN (gallium nitride) or the like are being developed. In a semiconductor chip having a III-V compound semiconductor layer, an interconnection layer containing Au (gold) as a main component (hereinafter referred to as an Au interconnection layer) is employed. This is because electrodes containing Au are employed as the ohmic electrodes in contact with the semiconductor layer or the electrodes such as gate electrodes.
Al and Au react with each other when the temperature reaches approximately 200° C., and form an intermetallic compound. Since this compound has high resistivity, the electric resistance at the contact portion between Al and Au becomes higher. This problem is known as “purple plague” (generation of AuAl2). To counter this problem, when a bonding wire containing Au as a main component (an Au wire) is connected to an interconnection layer containing Al as a main component (an Al interconnection layer), a pad containing Au as a main component (an Au pad) is formed on the Al interconnection layer, with a barrier layer being interposed in between, and the Au wire is connected onto the Au pad, as disclosed in Japanese Unexamined Patent Publication No. 59-210656. Also, a barrier layer can be formed between an Al interconnection layer and an Au interconnection layer, as disclosed in Japanese Unexamined Patent publication Nos. 11-162996 and 2006-173386. With this arrangement, a reaction between Al and Au can be prevented.
However, in a case where an Al pad 70 is formed on an Au layer 34 (an Au interconnection layer) formed on a substrate 10 of a compound semiconductor, with a barrier layer 72 being interposed between the Al pad 70 and the Au layer 34, and an Al wire 40 is connected to the Al pad 70, as shown in FIG. 1, a reaction between Al and Au is caused as will be described later.